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74LVTH543 Low Voltage Octal Registered Transceiver with 3-STATE Outputs
April 2000 Revised April 2000
74LVTH543 Low Voltage Octal Registered Transceiver with 3-STATE Outputs
General Description
The LVTH543 octal transceiver contains two sets of D-type latches for temporary storage of data flowing in either direction. Separate Latch Enable and Output Enable inputs are provided for each register to permit independent control of inputting and outputting in either direction of data flow. The LVTH543 data inputs include bushold, eliminating the need for external pull-up resistors to hold unused inputs. This octal registered transceiver is designed for low-voltage (3.3V) VCC applications, but with the capability to provide a TTL interface to a 5V environment. The LVTH543 is fabricated with an advanced BiCMOS technology to achieve high speed operation similar to 5V ABT while maintaining a low power dissipation.
Features
s Input and output interface capability to systems at 5V VCC s Bushold data inputs eliminate the need for external pullup resistors to hold unused inputs s Live insertion/extraction permitted s Power Up/Down high impedance provides glitch-free bus loading s Outputs source/sink -32 mA/+64 mA s Functionally compatible with the 74 series 543 s Latch-up performance exceeds 500 mA
Ordering Code:
Order Number 74LVTH543WM 74LVTH543MTC Package Number M24B MTC24 Package Description 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code.
Connection Diagram
Pin Descriptions
Pin Names OEAB, OEBA LEAB, LEBA CEAB, CEBA A0-A7 Description Output Enable Inputs Latch Enable Inputs Chip Enable Inputs Side A Inputs or 3-STATE Outputs B0-B7 Side B Inputs or 3-STATE Outputs
(c) 2000 Fairchild Semiconductor Corporation
DS012448
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74LVTH543
Logic Symbols
Functional Description
The LVTH543 contains two sets of D-type latches, with separate input and output controls for each. For data flow from A to B, for example, the A to B Enable (CEAB) input must be LOW in order to enter data from the A Port or take data from the B Port as indicated in the Data I/O Control Table. With CEAB LOW, a low signal on (LEAB) input makes the A to B latches transparent; a subsequent LOWto-HIGH transition of the LEAB line puts the A latches in the storage mode and their outputs no longer change with the A inputs. With CEAB and OEAB both LOW, the B output buffers are active and reflect the data present on the output of the A latches. Control of data flow from B to A is similar, but using the CEBA, LEBA and OEBA.
IEEE/IEC
Data I/O Control Table
Inputs Latch Status CEAB H X L X L LEAB X H L X X OEAB X X X H L Latched Latched Transparent -- -- Buffers High Z -- -- High Z Driving Output
H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Note: A-to-B data flow shown; B-to-A flow control is the same, except using CEBA, LEBA, and OEBA.
Logic Diagram
Please not that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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74LVTH543
Absolute Maximum Ratings(Note 1)
Symbol VCC VI VO IIK IOK IO ICC IGND TSTG Parameter Supply Voltage DC Input Voltage DC Output Voltage DC Input Diode Current DC Output Diode Current DC Output Current DC Supply Current per Supply Pin DC Ground Current per Ground Pin Storage Temperature Value -0.5 to +4.6 -0.5 to +7.0 -0.5 to +7.0 -0.5 to +7.0 -50 -50 64 128 64 128 -65 to +150 Output in 3-STATE Output in HIGH or LOW State (Note 2) VI < GND VO < GND VO > VCC Output at HIGH State VO > VCC Output at LOW State Conditions Units V V V V mA mA mA mA mA C
Recommended Operating Conditions
Symbol VCC VI IOH IOL TA t/V Supply Voltage Input Voltage HIGH Level Output Current LOW Level Output Current Free-Air Operating Temperature Input Edge Rate, VIN = 0.8V-2.0V, VCC = 3.0V -40 0 Parameter Min 2.7 0 Max 3.6 5.5 -32 64 85 10 Units V V mA C ns/V
Note 1: Absolute Maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditions is not implied. Note 2: IO Absolute Maximum Rating must be observed.
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74LVTH543
DC Electrical Characteristics
Symbol VIK VIH VIL VOH Parameter Input Clamp Diode Voltage Input HIGH Voltage Input LOW Voltage Output HIGH Voltage VCC (V) 2.7 2.7-3.6 2.7-3.6 2.7-3.6 2.7 3.0 VOL Output LOW Voltage 2.7 2.7 3.0 3.0 3.0 II(HOLD) II(OD) II Bushold Input Minimum Drive Bushold Input Over-Drive Current to Change State Input Current Control Pins Data Pins IOFF IPU/PD IOZL IOZH IOZH+ ICCH ICCL ICCZ ICCZ+ ICC Power Off Leakage Current Power Up/Down 3-STATE Output Current 3-STATE Output Leakage Current 3-STATE Output Leakage Current 3-STATE Output Leakage Current Power Supply Current Power Supply Current Power Supply Current Power Supply Current Increase in Power Supply Current (Note 5)
Note 3: An external driver must source at least the specified current to switch from LOW-to-HIGH. Note 4: An external driver must sink at least the specified current to switch from HIGH-to-LOW. Note 5: This is the increase in supply current for each input that is at the specified voltage level rather than VCC or GND.
TA =-40C to +85C Min 2.0 0.8 VCC - 0.2 2.4 2.0 0.2 0.5 0.4 0.5 0.55 75 -75 500 -500 10 1 -5 1 100 100 -5 5 10 0.19 5 0.19 0.19 0.2 Max -1.2
Units V V V V V V V V V V A A A A A A A A A A A A A mA mA mA mA mA
Conditions II = -18 mA VO 0.1V or VO VCC - 0.1V IOH = -100 A IOH = -8 mA IOH = -32 mA IOL = 100 A IOL = 24 mA IOL = 16 mA IOL = 32 mA IOL = 64 mA VI = 0.8V VI = 2.0V (Note 3) (Note 4) VI = 5.5V VI = 0V or VCC VI = 0V VI = VCC 0V VI or VO 5.5V VO = 0.5V to 3.0V VI = GND or VCC VO = 0.0V VO = 3.6V VCC < VO 5.5V Outputs HIGH A or B Port Outputs LOW Outputs Disabled VCC VO 5.5V Outputs Disabled One Input at VCC - 0.6V Other Inputs at VCC or GND
3.0 3.0 3.6 3.6 3.6 0 0-1.5V 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6
Dynamic Switching Characteristics
Symbol VOLP VOLV Parameter Quiet Output Maximum Dynamic VOL Quiet Output Minimum Dynamic VOL VCC (V) 3.3 3.3
(Note 6)
TA = 25C Conditions Max Units V V CL = 50 pF, RL = 500 (Note 7) (Note 7)
Min
Typ 0.8 -0.8
Note 6: Characterized in SOIC package. Guaranteed parameter, but not tested. Note 7: Max number of outputs defined as (n). n-1 data inputs are driven 0V to 3V. Output under test held LOW.
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74LVTH543
AC Electrical Characteristics
TA = -40C to +85C Symbol Parameter CL = 50 pF, RL = 500 VCC = 3.3V 0.3V Min tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ tPZH tPZL tPHZ tPLZ tW tS Propagation Delay Data to Outputs Propagation Delay LE to A or B Output Enable Time OE to A or B Output Disable Time OE to A or B Output Enable Time CE to A or B Output Disable Time CE to A or B Pulse Duration Setup Time LE LOW A or B before LE, Data HIGH A or B before LE, Data LOW A or B before CE, Data HIGH A or B before CE, Data LOW tH Hold Time A or B before LE, Data HIGH A or B before LE, Data LOW A or B before CE, Data HIGH A or B before CE, Data LOW tOSHL tOSLH Output to Output Skew (Note 8) 1.3 1.3 1.3 1.3 1.1 1.1 2.0 2.0 1.3 1.3 2.1 1.6 3.3 0.4 1.0 0.2 0.7 1.5 1.3 1.6 1.4 1.0 1.0 Max 4.4 4.6 5.4 5.8 5.5 6.1 5.7 5.3 5.9 6.2 5.8 5.4 VCC = 2.7V Min 1.3 1.3 1.3 1.3 1.1 1.1 2.0 2.0 1.3 1.3 2.1 1.6 3.3 0.4 1.5 0.2 1.2 0.6 1.5 0.5 1.6 1.0 1.0 ns ns ns Max 4.8 5.2 6.4 6.6 6.3 7.2 5.9 5.9 6.8 7.4 6.1 5.9 ns Units
ns
ns
ns
ns
ns ns
Note 8: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH).
Capacitance
Symbol CIN CI/O
(Note 9)
Parameter Conditions VCC = 0V, VI = 0V or VCC VCC = 3.0V, VO = 0V or VCC Typical 4 8 Units pF pF
Input Capacitance Input/Output Capacitance
Note 9: Capacitance is measured at frequency f = 1 MHz, per MIL-STD-883B, Method 3012.
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74LVTH543
Physical Dimensions inches (millimeters) unless otherwise noted
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package Number M24B
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74LVTH543 Low Voltage Octal Registered Transceiver with 3-STATE Outputs
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC24
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 7 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com
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